Self-aligned iii-v mosfet diffusion regions and silicide-like alloy contact

ABSTRACT

A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.

BACKGROUND

1. Technical Field

The present invention relates to semiconductor devices and moreparticularly to a self-aligned metal oxide semiconductor field effecttransistor (MOSFET) and integration methods.

2. Description of the Related Art

The performance enhancement of Si complementarymetal-oxide-semiconductor (CMOS) has traditionally been achieved bydevice scaling. However, performance enhancement and the reduction ofdevice size has become more challenging as devices achieve nanoscaledimensions. III-V compound semiconductors with high electron mobilityand low electron effective mass have been suggested as a new channelmaterial of n-metal-oxide-semiconductor field-effect transistors(n-MOSFETs). However, it is challenging to achieve III-V MOSFETs becausethere is no mature silicide-like process for III-V MOSFET junctions.

SUMMARY

A metal oxide semiconductor field effect transistor and method forforming the same include exposing portions on a substrate adjacent to agate stack, forming a dopant layer over the gate stack and in contactwith the substrate in the portions exposed and annealing the dopantlayer to drive dopants into the substrate to form self-aligned dopantregions in the substrate. The dopant layer is removed. A metalcontaining layer is deposited over the gate stack and in contact withthe substrate in the exposed portions. The metal containing layer isannealed to drive metal into the substrate to form self-aligned contactregions in a metal alloy formed in the substrate within the dopantregions. The metal layer is then removed.

A method for forming a metal oxide semiconductor field effect transistorincludes exposing portions on a p-type III-V substrate adjacent to agate stack; forming a dopant layer containing Ge over the gate stack andin contact with the substrate in the portions exposed; annealing thedopant layer to drive Ge dopants into the substrate to form self-aligneddopant regions in the substrate and to convert the p-type substrate ton-type in the dopant regions; removing the dopant layer; depositing ametal containing layer having Ni over the gate stack and in contact withthe substrate in the exposed portions; annealing the metal containinglayer to drive Ni into the substrate to form self-aligned contactregions in a metal alloy formed in the substrate within the dopantregions; and removing the metal containing layer.

A metal oxide field effect transistor device includes a III-V substrateand a source region and a drain region self-aligned to a gate stack andformed from diffused dopants with a dopant concentration sufficient tomake the source region and the drain region n-type. Contact regions areself-aligned with and formed within each of the source region and thedrain region, the contact regions being formed from a diffused metal.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a partially fabricated MOSFET deviceshowing exposed substrate regions for locating source/drain regions inaccordance with the present principles;

FIG. 2 is a cross-sectional view of the partially fabricated MOSFETdevice of FIG. 1 showing a dopant layer formed over the device inaccordance with the present principles;

FIG. 3 is a cross-sectional view of the partially fabricated MOSFETdevice of FIG. 2 showing dopants driven into the substrate at theexposed regions by an anneal process in accordance with the presentprinciples;

FIG. 4 is a cross-sectional view of the partially fabricated MOSFETdevice of FIG. 3 showing the dopant layer removed in accordance with thepresent principles;

FIG. 5 is a cross-sectional view of the partially fabricated MOSFETdevice of FIG. 4 showing a metal containing layer formed over the devicein accordance with the present principles;

FIG. 6 is a cross-sectional view of the partially fabricated MOSFETdevice of FIG. 5 showing metal driven into the substrate at the exposedregions by an anneal process in accordance with the present principles;

FIG. 7 is a cross-sectional view of the partially fabricated MOSFETdevice of FIG. 6 showing the metal layer removed in accordance with thepresent principles;

FIG. 8 is a cross-sectional view of the MOSFET device of FIG. 7 showinga cap layer removed from a gate structure in accordance with the presentprinciples; and

FIG. 9 is a block/flow diagram showing an illustrative method forfabricating a MOSFET with self-aligned source and drain regions andself-aligned contact pads fowled in the source and drain regions inaccordance with one illustrative embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present principles provide a transistor device preferably formed ina III-V substrate that has self-aligned source and drain regions. Inaddition, metal contacts are also self-aligned and formed on the sourceand drain regions. The transistor device may include a metal oxidesemiconductor field effect transistor (MOSFET). In one embodiment, ap-type substrate is employed. The source and drain regions may be formedby employing a self-aligned germanium layer, which is diffused into thesubstrate to convert the p-type substrate into an n-type source/drainregion.

It is to be understood that the present invention will be described interms of a given illustrative architecture having a wafer; however,other architectures, structures, substrate materials and processfeatures and steps may be varied within the scope of the presentinvention.

It will also be understood that when an element as a layer, region orsubstrate is referred to as being “on” or “over” another element, it canbe directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

A design for an integrated circuit chip may be created in a graphicalcomputer programming language, and stored in a computer storage medium(such as a disk, tape, physical hard drive, or virtual hard drive suchas in a storage access network). If the designer does not fabricatechips or the photolithographic masks used to fabricate chips, thedesigner may transmit the resulting design by physical means (e.g., byproviding a copy of the storage medium storing the design) orelectronically (e.g., through the Internet) to such entities, directlyor indirectly. The stored design is then converted into the appropriateformat (e.g., GDSII) for the fabrication of photolithographic masks,which typically include multiple copies of the chip design in questionthat are to be formed on a wafer. The photolithographic masks areutilized to define areas of the wafer (and/or the layers thereon) to beetched or otherwise processed.

Methods as described herein may be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a cross-sectional view of apartially fabricated transistor device is shown in accordance with oneexemplary embodiment. A substrate 100 includes a crystalline material,and preferably includes a III-V material such as GaAs, InGaAs, InP orother similar materials. In the present example, substrate 100 includesa p-type InGaAs material, although other materials may be employed. Afield dielectric 102, such as an oxide, is formed and patterned on thesubstrate 100 to define source and drain regions adjacent to a gatestack 104. In other designs, the field dielectric 102 may includeshallow trench isolation (STI) or other dielectric isolation regions.

The gate stack 104 may include a high-dielectric constant (high-k)material 110, such as, hafnium silicate, zirconium silicate, hafniumdioxide, zirconium dioxide, etc. Other dielectric materials may also beemployed and may be dependent on the design of the device. A gateconductor 108 is farmed on the high-k layer 110. The layers 108 and 110may be patterned, shaped or formed by known methods. A dielectric layer106 is formed over the layers 108 and 110. The dielectric layer 106 mayinclude a silicon nitride (SiN_(x)) material. Dielectric layer 106 maybe selectively deposited or selectively etched to cover layers 108 and110 as depicted.

Regions 105 include exposed portions of the substrate 100, and arepreferably formed adjacent to the gate stack 104. Regions 105 arecleaned of native oxide by employing an etch process. The etch processmay include, e.g., a HF or HCl wet etch.

Referring to FIG. 2, a dopant layer 112 is conformally formed over thetopography of the device. The dopant layer 112 preferably includesgermanium (Ge) or a compound including germanium. Other dopant layersmay also be employed such as layers containing silicon, sulfur, etc. Thedopant layer 112 may include a thickness of between about 0.1 nm (oneatomic layer) to about 100 nm. In one embodiment, a chemical vapordeposition (CVD) process may be employed to form the conformal dopantlayer 112. In one preferred embodiment, a plasma enhanced CVD (PECVD)process is employed. In one embodiment, dopant layer 112 may be formedafter dipping the device in the chemical solution (e.g., ammoniumsulfide).

Referring to FIG. 3, an anneal process is performed to drive-in dopantsfrom the dopant layer 112 into the substrate 100. The anneal process mayinclude a rapid thermal anneal (RTA) with temperatures of between about300 degrees C. to about 600 degrees C. for between about 1 minute toabout 40 minutes. The anneal process drives the dopants (e.g., Ge) intothe substrate 100 at locations where the dopant layer 112 is in contactwith the substrate 100. Dopant regions 114 and 116 are formed which inturn form source and drain regions of the device. The dopant regions 114and 116 are advantageously self-aligned since these regions 114 and 116are formed using a conformal layer 112 that contacts the substrate 100only at areas (105) opened up or patterned in earlier process steps. Ifthe substrate 100 includes a p-type substrate, the dopant regions 114and 116 that are produced are n-type. In other words, sufficient dopantconcentrations are provided in dopant regions 114 and 116 to exceed thep-type concentrations to make the regions n-type.

In one embodiment, a Ge layer was formed on a p-type InGaAs layer andsubjected to sheet resistance (R_(sh)) measurements for different annealprocess parameters. Table I shows the results.

TABLE I Temperature Time R_(sh) Process (degrees C.) (minutes)(ohms/square) Result RTA 400 10 1.03 × 10³ Ge starts to diffuse toreduce p-doping in substrate RTA 450 10 1.43 × 10³ Ge starts to diffuseto reduce p-doping in substrate RTA 500 10 0.80 × 10³ Ge furtherdiffuses into substrate to convert p-type to n-type RTA 550 10 0.66 ×10³ Ge further diffuses into substrate to convert p-type to n-type

Referring to FIG. 4, the dopant layer 112 is removed from the topologyof the device. In one embodiment where the dopant layer 112 includes Ge,a hydrogen peroxide (H₂O₂) wet etch is employed to remove the dopantlayer 112 and clean the surfaces of the device.

Referring to FIG. 5, self-aligned contact regions (120, 122 in FIG. 6)may be formed. A metal layer or metal containing layer 118 isconformally formed over the topology of the device. The metal layer 118is in contact with and is self-aligned to the underlying dopant regions114 and 116. The metal layer 118 may include Ni, although other metalsand alloys may be employed, such as W, Ti, Co, In, etc. The metal layer118 may be deposited using a CVD process or other suitable process. Themetal layer 118 may have a thickness of between about 1 nm to 100 nm.

Referring to FIG. 6, an anneal process is performed to drive in metalfrom the metal layer 118 into the dopant regions 114 and 116. The annealprocess may include a rapid thermal anneal (RTA) with temperatures ofbetween about 300 degrees C. to about 600 degrees C. for between about10 seconds to about 40 minutes. The anneal process drives the metal(e.g., Ni) into the dopant regions 114 and 116 of the substrate 100 atlocations where the metal layer 118 is in contact with the substrate100. Contact regions 120 and 122 are formed, which are disposed withinthe dopant regions 114 and 116 and self-aligned to openings 111 betweenthe field dielectric 102 and the gate stack 104. Contact regions 120 and122 provided a silicide-like contact, which overcomes the contactresistance and other issues of conventional devices.

In one embodiment, the metal layer 118 includes Ni and the substrateincludes InGaAs. The contact regions 120 and 122 preferably form analloy of the metal and the substrate materials. In one example, aNi—InGaAs alloy is formed by the anneal process. The contact regions 120and 122 will be employed in subsequent steps as landing pads formidlevel contacts (not shown) to make electrical connections with highermetal layers.

Referring to FIG. 7, the metal layer 118 is removed from the topology ofthe device. The metal layer 118 may be removed by a wet etch process,e.g., an HCl wet etch.

Referring to FIG. 8, layer 106 is etched or polished to remove a capover the gate stack 104 to expose gate conductor 108. By removing thecap, spacers 126 are formed adjacent to the gate stack 104. An n-MOSFETdevice 130 is formed. Subsequent processing may include forming metallayers and other features.

Referring to FIG. 9, a block/flow diagram illustratively shows a methodfor fabricating a MOSFET with self-aligned source and drain regions andself-aligned metal contacts in accordance with the present principles.It should also be noted that, in some alternative implementations, thefunctions noted in the blocks may occur out of the order noted in thefigures. For example, two blocks shown in succession may, in fact, beexecuted substantially concurrently, or the blocks may sometimes beexecuted in the reverse order, depending upon the functionalityinvolved.

In block 202, portions of a substrate adjacent to a gate stack orstructure are exposed. This may include patterning a field dielectriclayer or other mask and opening up portions adjacent to the gate stack.A clean etch (e.g., HF, HCl, etc.) may be performed to remove nativeoxide from the exposed areas of the substrate. The substrate preferablyincludes a III-V substrate, such as, e.g., GaAs, InGaAs, InP, etc. Inblock 204, a dopant layer is formed over the gate stack and in contactwith the substrate in the portions exposed. This may include a PECVDprocess which deposits a Ge layer or a layer containing Ge. In block206, the dopant layer is annealed to drive dopants into the substrate tofour self-aligned dopant regions in the substrate. The dopant layerpreferably includes Ge and the anneal process may include annealing witha rapid thermal anneal having a temperature of about 500 degrees forabout 10 minutes. Other temperatures and times may be employed as well.

In block 208, in one embodiment, sufficient dopant concentration isprovided from the dopant layer to convert the dopant regions from afirst polarity to an opposite polarity. In one example, the substrateincludes a p-type substrate, the dopants include n-type dopants (e.g.,Ge) and the dopant regions are converted to n-type regions. In block210, the dopant layer is removed. The dopant layer is preferably removedimmediately after the anneal process by a wet etch.

In block 212, a metal containing layer is deposited over the gate stackand in contact with the substrate in the exposed portions. In block 214,the metal containing layer is annealed to drive metal into the substrateto form self-aligned contact regions as a metal alloy formed in thesubstrate within the dopant regions. In one embodiment, the substrateincludes InGaAs, the metal layer includes Ni and the metal alloyincludes a Ni—InGaAs alloy. In block 216, the metal layer is removed. Inblock 218, middle end of line and back end of line processing iscontinued as in known in the art.

Having described preferred embodiments for a self-aligned III-V MOSFETdiffusion regions and silicide-like alloy contact (which are intended tobe illustrative and not limiting), it is noted that modifications andvariations can be made by persons skilled in the art in light of theabove teachings. It is therefore to be understood that changes may bemade in the particular embodiments disclosed which are within the scopeof the invention as outlined by the appended claims. Having thusdescribed aspects of the invention, with the details and particularityrequired by the patent laws, what is claimed and desired protected byLetters Patent is set forth in the appended claims.

1. A method for forming a metal oxide semiconductor field effecttransistor, comprising: exposing portions on a substrate adjacent to agate stack; forming a dopant layer over the gate stack and in contactwith the substrate in the portions exposed; annealing the dopant layerto drive dopants into the substrate to form self-aligned dopant regionsin the substrate; removing the dopant layer; depositing a metalcontaining layer over the gate stack and in contact with the substratein the exposed portions; annealing the metal containing layer to drivemetal into the substrate to form self-aligned contact regions in a metalalloy formed in the substrate within the dopant regions; and removingthe metal layer.
 2. The method as recited in claim 1, wherein forming adopant layer includes forming a layer containing Ge.
 3. The method asrecited in claim 1, wherein the substrate includes a III-V material. 4.The method as recited in claim 1, wherein annealing the dopant layer todrive dopants into the substrate to form self-aligned dopant regionsincludes providing sufficient dopant concentration to convert the dopantregions from a first polarity to an opposite polarity.
 5. The method asrecited in claim 4, wherein the substrate includes a p-type substrateand the dopants include n-type dopants and the dopant regions areconverted to n-type regions.
 6. The method as recited in claim 1,wherein exposing portions on a substrate adjacent to a gate stackincludes patterning a field dielectric to expose the substrate.
 7. Themethod as recited in claim 1, wherein the substrate includes InGaAs andthe metal layer includes Ni and the metal alloy includes a Ni—InGaAsalloy.
 8. The method as recited in claim 1, wherein the dopant layerincludes Ge and the step of annealing the dopant layer includesannealing with a rapid thermal anneal having a temperature of about 500degrees for about 10 minutes.
 9. The method as recited in claim 1,wherein removing the dopant layer includes performing an etchimmediately after the step of annealing the dopant layer.
 10. A methodfor forming a metal oxide semiconductor field effect transistor,comprising: exposing portions on a p-type III-V substrate adjacent to agate stack; forming a dopant layer containing Ge over the gate stack andin contact with the substrate in the portions exposed; annealing thedopant layer to drive Ge dopants into the substrate to form self-aligneddopant regions in the substrate and to convert the p-type substrate ton-type in the dopant regions; removing the dopant layer; depositing ametal containing layer having Ni over the gate stack and in contact withthe substrate in the exposed portions; annealing the metal containinglayer to drive Ni into the substrate to form self-aligned contactregions in a metal alloy formed in the substrate within the dopantregions; and removing the metal containing layer.
 11. The method asrecited in claim 10, wherein the substrate includes GaAs.
 12. The methodas recited in claim 10, wherein exposing portions on a substrateadjacent to a gate stack includes patterning a field dielectric toexpose the substrate.
 13. The method as recited in claim 10, wherein thesubstrate includes InGaAs and the self-aligned contact regions include aNi—InGaAs alloy.
 14. The method as recited in claim 10, whereinannealing the dopant layer includes annealing with a rapid thermalanneal having a temperature of about 500 degrees for about 10 minutes.15. The method as recited in claim 10, wherein removing the dopant layerincludes performing an etch immediately after the step of annealing thedopant layer. 16.-20. (canceled)